Recently, portable electronic equipment such as mobile telephones and non-volatile semiconductor memory media such as IC memory cards have been downsized, and there have been increasing demands for reducing the number of parts used in the equipment and media and downsizing thereof. Therefore, in the semiconductor industry, packaging technologies for integrated circuits (ICs) have been advancing to meet requirements for miniaturization and mounting reliability. For example, the requirement for miniaturization results in acceleration of technological development for a package having a similar size in relation to a semiconductor chip. Further, the requirement for mounting reliability places importance on packaging technologies that are capable of enhancing efficiency of a mounting process and improving mechanical and electrical reliability after the mounting process is completed. Thus, there have been considerable activities in the development of efficiently packaging a semiconductor chip. As packages that meet the demands, there are a chip scale package (CSP) having a package size substantially equal to that of the semiconductor chip, a multi-chip package (MCP) in which multiple semiconductor chips are incorporated into a single package, and a package-on-package (POP) in which multiple packages are stacked and combined into a single-piece member.
In pace with the development of technology, in response to an increase in storage capacity required for memory and the like, stacked type semiconductor devices (multichip devices) have been proposed which have semiconductor integrated circuit chips stacked together. Namely, there is provided a stacked type semiconductor device formed of at least two semiconductor integrated circuit devices stacked, each having a specification and including a semiconductor integrated circuit chip, wherein each of the semiconductor integrated circuit devices includes a conductor that penetrates the semiconductor integrated circuit device, and the semiconductor integrated circuit devices are electrically connected by the conductors and a value of the specification, excluding a size, of the uppermost semiconductor integrated circuit device or the lowermost semiconductor integrated circuit device is maximum or minimum. Consequently, the stacked type semiconductor device has a plurality of chips stacked in a vertical direction. In the stacked type semiconductor device, the chips are electrically connected together via, for example, through plugs that penetrate the chips. Thus, to select a desired one of the stacked memory chips of the same structure is an important task. If a stacked type semiconductor device is manufactured, chips may be individually subjected to operation tests so that only normal chips can be sorted out and stacked.
One of the technologies to offer vertical connection is called Through-Silicon-Via (TSV) which has emerged as a promising solution in 3-D stacked devices. It is a technology where vertical interconnects are formed through the wafer to enable communication among the stacked chips.
As shown in FIG. 1, it shows a schematic diagram of a conventional 2D circuit stacking architecture. The architecture includes a stacked multi-layer chips and a logic control circuit layer. The multi-layer (layer 1˜layer N) chips are stacked by bottom-up structure, and each chip layer comprises its respective memory array, timer and contact pads. The chips between adjacent layers are electrically connected with each other via a TSV (Through Silicon Via). For example, the first chip layer contains a memory array 103, a timer 104 and contact pads 105, and the N-th chip layer includes a memory array 107, a timer 108 and contact pad 109. Between the first˜(to) N-th chip layer, the contact pads 109 and the contact pads 105 are electrically connected with each other via a TSV 106, respectively. The logic control circuit layer includes a logic control circuit 100 and contact pads 101. The contact pads 101 are electrically connected to the contact pads 105b via TSV 102. The logic control circuit 100 can be electrically connected to the above-mentioned contact pads to control the chip on the first chip layer to the N-th chip layer. In the direct stacking architecture, each chip layer includes its respective timer and decoder, and each chip layer shares the same I/O bus. The functional diagram of the above-mentioned 2D circuit scheme is shown in FIG. 2. Each chip layer includes its respective memory array (110, 120) and a local sense amplifier (111, 121), a timing control circuit (117, 127) and a logic control circuit (118, 128). The timing control circuit (117, 127) includes a local timer (112, 122) and a local bias (113, 123), and the logic control circuit (118, 128) includes a command decoder (114, 124), a command latch circuit (115, 125) and an input/output (I/O) latch circuit (116, 126). In this example, self-timing control circuit is proposed to improve the circuit yield. Purpose for such circuit design is desired to track the variation of process, voltage and temperature so that the self-timing can be automatically adjusted based-on different characteristic of each chip, and thereby improving the yield effectively.
US patent publication No. 2010/0020583A1 discloses stacked memory module and system. As shown in FIG. 3, it shows a block diagram of a three dimensional memory system. The three dimensional memory module includes a master chip and the slave chips, the master chip includes a master memory core, state circuits, an internal I/O (input/output), an external I/O (input/output) and a tracking circuit, and the slave chips include respective slave memory cores, state circuits, an internal I/O (input/output), respectively. The master chip is electrically connected to the slave chip via the internal I/O. The respective state circuits indicate a respective command execution state for the master and slave cores, respectively. The respective command execution state indicates whether a respective command such as a read, write, active, or refresh command has been executed by the respective memory core. In the master-slave scheme of the proposed patent, the tracking circuit is configured in the master chip layer, and the state circuits are configured in the slave chip layer. Therefore, the operation status of the slave chip may be sent to the tracking circuit of the master chip by the state circuit, to achieve the purpose of stackable memory by the tracking circuit.
One of the related article may refer to IEEE, JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 1, JANUARY 2010, entitled: “8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology”. In the article, a 3-D DRAM with TSVs is proposed which overcomes the limits of conventional module approaches. As shown in FIG. 4, the master-slave chip architecture includes a master chip and slave chips, wherein the master chip includes a memory core 143, read/write control circuit 147, I/O buffer 148 and contact pads 149, and each of slave chips includes a memory core (140, 141, 142) and core test logic circuit (144, 145, 146). In the proposed patent by Samsung Electronics, the read/write control circuit 147 is configured in the master chip layer, and the test circuit is configured in the slave chip, and thereby controlling the entire circuit by the master chip layer.
In data communication systems, it typically utilizes a transmitting device that operates under control of a first clock and an independent receiving device that operates under control of a second clock. In general, the transmitting device and the receiving device have a clock rate difference. This clock rate difference causes the receiver to see the incoming data at either faster or slower than expected, hereafter referred to as “timing drifting”. For packet based communication systems, if the amount of the maximum possible timing drift during the packet is much smaller than a symbol period, then this clock rate difference can be ignored. U.S. Pat. No. 7,003,056 disclosed a symbol timing tracking and method, and it uses timing tracking to correct timing drifting due to the difference in frequency of a transmitter clock and a receiver clock. With the timing tracking, correlation values of three consecutive samples are calculated using the receive signal and the recovered symbols and then summed. Further, SRAMs are widely used in applications where speed is of primary importance, such as the cache memory typically placed proximate to the processor or Central Processing Unit (CPU) in a personal computer. However, the timing of its internal circuitry may critically affect the speed and efficiency of the SRAM. For example, the bit line pre-charge interval comprises an appreciable portion of the read/write cycle time, and sense amplifier usage contributes significantly to the overall power consumption of the SRAM. In early SRAM memory designs, all read/write cycle timing was based on an externally generated clock signal. Another related art disclosed in U.S. Pat. No. 6,643,204 which includes self-time circuit for reducing the write cycle time in a semiconductor memory. A “dummy” memory cell having the same timing requirements as the functional cells, and associated write logic are added to the standard circuitry of the memory device. The dummy write cell receives the same control signals used to write data to the functional cells of the memory, and is configured to issue a completion signal when a write access is concluded, causing the write cycle to be terminated. The circuit and method permits write cycle time to be reduced to the lowest practical value, independently of the read cycle time. This potentially increases the overall operating speed of the memory device.
As mentioned above, some stacked memory architectures have been proposed. However, there are still some technical difficulties and bottlenecks to be overcome, such as wire (trace) RC delay, increased leakage current and the process issues. Furthermore, the process development for 3D chip is in embryonic stage, there are some issues to be resolved, for example through silicon via (TSV) overloading resulting in poor performance, or larger area making poor efficiency. In the circuit scheme of multi-layer stacking chips, the power dissipation accumulated by the leakage current can not be underestimated. Based-on these issues to be improved, the present invention proposes a new type stacked structure and a circuit mechanism to reduce the leakage current to address and improve the above issues.